1. Field
Embodiments of the present invention are related to communication receivers and, in particular, to receivers that include voltage-controlled oscillators (VCO) and low-noise amplifiers (LNA).
2. Discussion of Related Art
Wireless communication systems commonly include cellular phones, radios, and radar systems, for example. A typical wireless system includes a receiver that receives a signal carried on an electromagnetic wave, such as a radio frequency (RF) signal.
The ever-increasing interest in wireless communication systems also is emphasizing higher levels of integration, more complex functionalities and lower cost in integrated circuit (IC) implementations. Recently, complementary metal oxide semiconductor (CMOS) has emerged as viable alternative for RF and microwave integrated circuit (MIC) designs owing to the continued scaling of minimum feature size. The ability to integrate complex digital signal processing functions makes CMOS an attractive candidate for system-on-chip (SOC) solutions. System-on-chip necessitates the implementation of different analog building blocks on the same die together with the large-scale digital circuits required by the complex digital signal processing (DSP) functions. Unfortunately, parasitic coupling in silicon technology, especially through the conductive silicon substrate, makes it possible for digital switching noise to corrupt the weak analog and RF signals.
FIG. 1 is a simplified schematic diagram of a wireless receiver 100. The receiver 100 includes an antenna 102 coupled to a bandpass filter 104. The bandpass filter 104 is coupled to a low-noise amplifier (LNA) 106, which is coupled to a mixer 108. The mixer 108 is coupled to a low-pass filter (LPF) 110, which is coupled to an intermediate frequency (IF) amplifier 112. The IF amplifier 112 is coupled to an analog-to-digital converter (ADC) 114.
The receiver 100 may operate as follows. An RF signal may be transmitted to the receiver 100 and may arrive at the antenna 102. The bandpass filter 104 may filter out all frequencies in the RF signal that do not fall within its pass band. The LNA 106 may amplify the filtered signal and suppresses noise contributed by the filter 104. The mixer 108 may down-convert the filtered and amplified signals to a lower intermediate frequency (IF). The low pass filter (LPF) 110 may low-pass the output signal from the mixer 108. The IF amplifier 112 may amplify the signal from the LPF 110. The ADC 114 may convert the output of the IF amplifier 112 to a digital base band signal, such as to an audio frequency, for example.
A role that the LNA 106 plays in the receiver 100 is appreciated by considering the Friis equation, which states that noise from blocks following the LNA 106, typically the mixer 108, is suppressed by the gain of the LNA [1] [2] [3]. Therefore, low noise and high gain are the most important figures of merit of an LNA. In addition, LNA design involves tradeoffs between linearity, stability, input matching, and power consumption.
Two popular topologies are widely used to implement a LNA such as the LNA 106, namely, the common-gate configuration and common-source configuration. Common-gate topology has such advantages as lower power consumption, easier input matching, less sensitivity to parasitic capacitances, and better reverse isolation compared to those of common-gate topology. However, the higher noise figure and lower gain of the common-gate configuration impede it from being widely used. Instead, a common-source amplifier with inductive degeneration is a more popular choice in designing LNA circuits.
Phase-locked loops (PLL) are widely used in many applications, including radio frequency synthesis, clock generation and clock and data recovery (CDR) circuits. Shown in FIG. 2 is a typical block diagram of a PLL 200 in which the output ωLO of the PLL 200 can be used as an input to the mixer 108. The illustrated PLL 200 includes a reference frequency source 202 coupled to a phase-frequency detector (PFD) 204, whose output is coupled to a loop filter 206. The loop filter 206 is coupled to a voltage-controlled oscillator (VCO) 208, which is coupled to a divide-by-N circuit 210. The output of the divide-by-N circuit 210 is coupled to a second input of the PFD 204.
In operation, the PFD 204 detects the phase and/or frequency difference between the reference frequency supplied by the reference frequency source 202 and the output of divide-by-N circuit 210 and generates a DC voltage proportional to the difference. The loop filter 206 attenuates high frequency components and extracts the DC information from the PFD 204 output signal. The VCO 208 generates an oscillating waveform at the desired frequency according to the voltage 212 output from the loop filter 206.
In a PLL, all the constituent circuit blocks such as the VCO, frequency divider, loop filter, charge pump, and PFD contribute phase noise at the output. Typically, it is often the case that the VCO is the dominant source of phase noise. Therefore, extensive effort has been invested in improving the phase noise performance of oscillators.